Plasma display panels (PDPs) are one type of gas discharge panel, and they are attracting attention as the display panels of the future due to their short depth and the comparative ease with which screen size can be increased. At present, 60-inch class models are available on the market.
FIG. 28 is a partial cross-sectional perspective view of a main structure of a conventional AC-type surface discharge PDP. In FIG. 28, the z direction corresponds to a thickness of the PDP, and the xy plane corresponds to a plane that is parallel with a panel surface of the PDP. As shown in FIG. 28, PDP 1 is structured from a front panel FP and a back panel BP that are arranged with main surfaces facing each other.
On a main surface of a front panel glass 2 that forms a substrate of front panel FP, plural pairs of display electrodes 4 and 5 (scan electrode 4, sustain electrode 5) are structured in the x direction, so as to conduct a surface discharge between each pair of display electrodes 4 and 5. Here, display electrodes 4 and 5 are, for example, made from a mixture of Ag and glass.
Scan electrodes 4 are each electrically independent, and power is supplied separately. Sustain electrodes 5 are all electrically connected to the same potential.
On the main surface of front panel glass 2 on which display electrode 4 and 5 are arranged, a dielectric layer 6 made from an insulating material, and a protective layer 7 are coated in the stated order.
On a main surface of back panel glass 3 that forms a substrate of back panel BP, a plurality of address electrodes 11 are arranged in a stripe pattern so as to extend in the y direction. These address electrodes are made from a mixture of Ag and glass.
On the main surface of back panel glass 3 on which address electrodes 11 are arranged, a dielectric layer 10 made from an insulating material is coated. On dielectric layer 10, barrier ribs 8 are arranged to correspond to the gap between two adjacent address electrodes 11. On the walls of barrier ribs 8 and on the surface of dielectric layer 10 between any two adjacent barrier ribs 8 are formed phosphor layers 9R, 9G and 9B corresponding to the colors red (R), green (G), and blue (B).
Here, a width in the x direction of phosphor layers 9R, 9G and 9B is shown in FIG. 28 as being the same, although in order to achieve brightness balance among the colors, the phosphor layers corresponding to one or more of the colors may be widened in comparison to the other phosphor layers.
Front panel FP and back panel BP structured as described above are positioned facing one another so that a lengthwise direction of address electrodes 11 is orthogonal to a lengthwise direction of display electrodes 4 and 5.
Front panel FP and back panel BP are sealed together around their periphery using a sealing material such as frit glass, and the space between the two panels is made airtight.
The space between the sealed panels is then filled at a predetermined pressure (conventionally approx. 40 kPa-66.5 kPa) with a discharge gas that includes Xe.
As a result, the space portioned between dielectric layer 6, phosphor layers 9R, 9G and 9B, and adjacent barrier ribs 8 in the sealed front and back panels is formed as discharge space 38. Furthermore, the areas where a pair of display electrodes 4 and 5 extend orthogonally across an address electrode 11 with a discharge space 38 therebetween are formed as cells (not depicted) that relate to image display. Here, FIG. 29 shows a matrix formed from plural pairs of display electrodes 4 and 5 (N rows) and a plurality of address electrodes (M columns) in a PDP.
When the PDP is driven, a discharge is initiated between the address electrode and one of the display electrodes in each cell, short-wave ultraviolet rays are generated as a result of a discharge that occurs between the display electrodes in each pair, and phosphor layers 9R, 9G and 9B illuminate visible light when struck by the ultraviolet rays. Image display is thus achieved.
Next, a drive method for a prior art PDP will be described in detail with reference to FIGS. 30 and 31.
FIG. 30 is a conceptual block view of an image display device that uses the prior art PDP, and FIG. 31 shows exemplary drive waveforms applied to the electrodes in the panel.
As shown in FIG. 30, for driving the PDP, PDP display apparatus includes a frame memory 100, an output processing circuit 110, an address electrode drive circuit 120, a sustain electrode drive circuit 130, and a scan electrode drive circuit 140. Electrodes 4, 5 and 11 are connected to circuits 140, 130 and 120, respectively, and circuits 120, 130 and 140 are connected to output processing circuit 110.
When the PDP is driven, image information from an external source is temporality stored in frame memory 100, and then in accordance with timing information, the stored image information is sent from frame memory 100 to output processing circuit 110. Output processing circuit 110, which is driven in accordance with the image information and timing information, issues instructions to circuits 120, 130 and 140 to apply pulse voltages to electrodes 4, 5 and 11, and image display is achieved as a result.
As shown in FIG. 31, according to this drive method for the PDP, image display is achieved by conducting a consecutive sequence of periods that include an initialization period, a write period, a sustain period, and an erase period.
To display a television image, the image according to the NTSC standard is structured from 60 fields per second. Plasma display panels are fundamentally only capable of expressing the two gradations of ON and OFF. Thus to express the intermediate colors, the ON period of each of the colors red (R), green (G) and blue (B) is time divided, a single field is divided into a plurality of subfields, and the intermediate colors are expressed by varying the combination of subfields.
FIG. 32 shows a method for dividing a single field into subfields to express 256 gray levels in a prior art AC-type PDP. Here, the weighting of the subfields is conducted in binary, with the ratio of sustain pulses applied during the sustain period of the subfields being 1, 2, 4, 8, 16, 32, 64 and 128, respectively. The 256 gray levels are expressed by varying the combination of these eight bits.
When the PDP is driven, an initialization pulse is applied in each subfield to scan electrodes 4, and the wall charge in the cells of the panel is initialized. Next, writing is conducted by applying a scan pulse to the upper most (i.e. at the top of the display) scan electrode in the y direction, and applying a write pulse to address electrodes in cells for display that include the upper most scan electrode. As a result, wall charge is stored on the surface of dielectric layer 6 in cells corresponding to the scan and address electrodes to which the scan and address pulses are applied.
Next, in the same manner as described above, a scan pulse is applied respectively to the scan electrode subsequent to the uppermost scan electrode, and a write pulse is applied to address electrodes in cells for display, thus storing wall charge on the surface of dielectric layer 6 corresponding to these cells. This process is conducted for all of the display electrodes in the panel, and this results in the writing of one screen of latent image.
Next, a sustain discharge is conducted by grounding address electrodes 11 and applying a sustain pulse alternately to scan electrodes 4 and sustain electrodes 5. A discharge is generated in cells storing wall charge on the surface of dielectric layer 6 from the write discharge, because of the potential of the surface of dielectric layer 6 rising above a discharge sparking voltage, and for the duration (sustain period) that the sustain pulse is applied, a sustain discharge occurs in display cells to which the write pulse was selectively applied. In each of the cells during the sustain discharge, a discharge is initiated between the address electrode and one of the scan electrode and the sustain electrode, and this discharge results in the generation of short-wave ultraviolet rays (Xe resonance line; wavelength approx. 147 nm), which in turn strike and excite phosphor layers 9R, 9G, and 9B to illuminate visible light. Image display is achieved as a result.
An unstable discharge is then generated by applying an erase pulse having a narrow pulse width, and this serves to eliminate the wall charge and erase the image.
Today, however, there is a demand for electrical appliances that suppress power consumption as much as possible, and thus interest is focused on reducing the power required to drive PDPs. The demand for technology that realizes power reductions is all the more urgent given the tendency for increased power consumption in recently developed PDPs, due to the larger screen sizes and image definition improvements. Moreover, the demand for reliable image display capabilities in PDPs remains a fundamental issue.
As such, the aim is to achieve reductions in power consumption while at the same time maintaining reliable driving and luminescence brightness levels. In other words, improvements in luminescence efficiency are desired.
In order to improve luminescence efficiency, research is currently being conducted, for example, into improving the efficiency with which phosphors convert ultraviolet rays into visible light, although still further improvements in luminescence efficiency are desirable.
Furthermore, in order to suppress the discharge voltage to an appropriate level while at the same time increasing panel brightness, conventional technology (e.g. see Japanese patent no. 2,734,405) has involves the use, for example, of electrode configurations in which openings are provided, or in which the display electrodes are partially divided. However, depending on the surface area of the divided electrodes, the discharge voltage maybe suppressed too much, or brightness may be reduced. The above problems are further exacerbated when there is a variation in the size of the electrodes.
To counter these problems, current flow can be maintained by providing wide bus electrodes, although because the bus parts themselves block the generated luminescence, the problem becomes one of maintaining brightness levels. Also, when the width of bus electrodes or a surface area of electrodes positioned farthest from a main electrode gap is increased, not only is the distance between adjacent cells reduced, but the accumulation of wall charge tends to occur away from the center of the cells, and thus crosstalk and other undesirable discharges can easily occur. Furthermore, reduction in the electrode surface area results in increases in the resistance value, and this can lead to problems of power loss.
Furthermore, with conventional structures, a lot of external light is reflected onto the panel surface because of the phosphor layers and barrier ribs being white, and thus, even when the darkroom contrast ratio is 500:1 or greater, the photopic contrast ratio drops to around 10:1. Conventional methods of solving this problem involve increasing the contrast by providing a black area (i.e. a so-called “black stripe”) between adjacent discharge cells so as to increase the black surface area ratio (blackness ratio) per cell, or increasing the contrast ratio by providing a filter on the display surface.
Conventional display electrodes are, however, divided by function into transparent electrodes for increasing the amount of visible light recovered from the discharge, and bus electrodes for reducing the wiring resistance within the panel, and thus a common technique used to increase the contrast ratio is coloring the area between adjacent cells (including the bus electrode surface facing the substrate) black. The only way of coloring the surface of the bus electrodes facing the substrate black is either to use an electrode material that makes an substrate-side of the bus electrodes black, or to form a black material with dielectric qualities between the transparent electrode and the bus electrode as a black stripe. Furthermore, in order to also color the area between adjacent bus electrodes black and increase the blackness ratio, it is necessary to form a black material having different insulating qualities between the adjacent bus electrodes. Consequently, achieving a desired blackness ratio (contrast) leads to complications in the manufacturing process and increased material costs.